Semiconductor constructions may be fabricated to have multiple levels of circuitry stacked over a semiconductor base. Some of the levels may be densely packed with repeating circuit elements, such as, for example, levels containing arrays of memory devices. The memory arrays may be a substantial portion of the circuitry, such as, for example, if the semiconductor constructions correspond to DRAM or flash chips. Alternatively, the memory arrays may be a relatively minor portion of the circuitry, such as, for example, in applications in which the arrays correspond to cache within processors or other semiconductor constructions which are primarily logic.
It can be desired to electrically couple two different levels of circuitry that are on opposing sides of a densely patterned intermediate level, without coupling to the intermediate level. Thus, it can be desired to form an electrical interconnection which passes through the intermediate level, without shorting to the intermediate level. Present methods of fabrication may attempt to achieve such electrical interconnection by breaking a circuit pattern within the intermediate level to create a path for the electrical interconnection. However, such methods can damage the circuitry remaining within the intermediate level, which can negatively impact device performance characteristics, and in some cases lead to device failure.
Sometimes dummy features are formed along the intermediate level in locations where interconnections will pass through the intermediate level, and then openings are etched through the dummy features to provide paths for the electrical interconnections. However, the introduction of dummy features creates a new set of complications for a fabrication process, consumes valuable semiconductor real estate that could otherwise be utilized for high-density circuitry, and in some cases does not adequately protect the intermediate level from adverse consequences during formation of electrical interconnections through such intermediate level.
It is desired to develop new methods for forming electrical interconnections passing through densely patterned levels of semiconductor constructions.